Method and apparatus for bandwidth limited binary signals

ABSTRACT

In a method for limiting the bandwidth of a selected binary signal (B), there is produced a modulated digital signal (D) which presents a continuous series of changes in signal level. The two occurrent logic states (1,0) are each represented by a respective symmetrical pulse train, wherein the frequencies f1, f2 of the pulse trains are mutually different. The higher frequency f2 is equal to the number of bits transmitted each second divided by two herz. The transition between the two pulse trains is arranged so that the integral of the resultant signal will be zero within the duration of three of four data bits. In a preferred embodiment of a coder and decoder each include a code word counter which, together with a combinatory logic circuit (code word table) activates or is activated by a shift register for transmitting or receiving respectively the modulated digital signal.

TECHNICAL FIELD

The present invention relates to a method of limiting the bandwidth of aselected binary signal, by generating a digital signal which exhibits acontinuous series of changes in signal level. The two logic states areeach represented by a respective pulse train, which have the respectivefrequencies f1 and f2.

BACKGROUND ART

Several different digital signal transmission methods are described inthe literature. For example, various textbooks describe methods whichare generally known under the designations NRZ-coding, Bifas-coding andDM-coding. See, for instance, the product catalogue "Z16C30 CMOS USCUniversal Serial Controller", May 1989, ZILOG Inc., Campbell, Calif.95008-6609, U.S.A., page 8.

The most simplest and the most common coding method is the NRZ method(Non Return to Zero), which implies that a logic one is represented by ahigh signal and a logic zero is represented by a low signal (or viceversa). NRZ-signalling requires a transmission channel that has abandwidth of from 0 to 1/TB Hz, where TB is the duration of a data bitin seconds. The NRZ-code has a large direct voltage (DC) component,which renders it unsuitable when the lower band limit differs from 0.Neither does NRZ coding ensure that a minimum time lapse between twomutually sequential changes in signal level will always be present inany given binary data signal, which means that a clock signalrepresenting the position of each data signal bit, cannot be obtainedfrom the data signal, but must be transmitted on a separate channel.

Another method is the Bi-phase code method. In the Bi-phase code, atleast one and at most two changes in signal level always occur with eachbit interval. Although this enables the clock signal to be obtained fromthe coded signal, the bandwidth of the transmission channel is increasedto 0-2/TB. The most serious drawback with the Bi-phase codes is that theupper band limit is twice the upper band limit with NRZ signalling.

The Manchester code is a variant of Bi-phase modulation, also known asBiphase-level, where a logic one is coded as 1/2TB high signal levelfollowed by 1/2TB low signal level and a logic zero is coded as 1/2TBlow signal level followed by 1/2TB high signal level. The Manchestercode is therefore dependent on polarity.

The DM-code (Delay Modulation) or the Miller code is another methodwhich, similar to the Bi-phase code, enables the clock signal to beregenerated from the modulated data signal, but lacks the drawback ofthe Bi-phase code with respect to the high upper band limit. The DM-codemodulated data signal, however, is completely void of direct voltagecomponents. In DM, a logic one is coded as a change in signal level inthe middle of the bit interval and a logic zero is coded as a change insignal level at the end of the bit interval, only if it is followed by afurther zero.

Both the Manchester codes and the DM codes also have the drawback thatin the case of an infinite stream of ones or zeroes, the modulated datasignal is identical to the phase shift of solely 1/2 data bit. Thisresults in a synchronization problem, since it is necessary for thereceiver (the decoder) to be aware of the phase position in order to beable to decode the modulated signal correctly.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a method which willavoid the drawbacks associated with the known methods and to modulate adigital signal so that the resultant signal will be more suited fortransmission over bandwidth limited media, for example a cable.

This is achieved in accordance with the invention in that thefrequencies f1, f2 of the pulse train of the modulated digital signalare mutually different, and in that the higher frequency, f2, is equalto the number of data bits per second divided by two (1/2TB). Thetransition between the two pulse positions is arranged so that theintegral or Run Length Digital Sum (RDS) of the resultant signal will beequal to zero within the duration of four transmitted data bits (4TB).

The modulated signal is coded differentially, so that it is thetransitions or junctions from one signal level to the other that areinformation carrying (and not the actual levels themselves). Thisimplies a polarity dependency.

In a particularly preferred embodiment of the inventive method, in whichthe selected binary input signal is an NRZ-signal, the following codingtable is used for translating the selected NRZ-signal:

    ______________________________________                                        Coding Table                                                                   ##STR1##                                                                     ______________________________________                                         ##STR2##                                                                     ______________________________________                                         + = one or more zeroes: The first 3 zeroes are coded in accordance with       the code word, whereafter there remains at least one further zero.       

The code word is twice the length of the coded binary bit pattern, suchthat 2 bits for each NRZ-bit are used for modulating the recordingmedium. The code word modulates the recording means so that a logic one(1) will result in a change in signal level after the bit interval, andso that a logic zero (0) will result in no change in signal level.

The code word can also be expressed as a trinary value (with the base3). When the code word is expressed with the base 3, correspondingreasoning is then: The code word modulates the recording means such thata one (1) results in a change in signal level in the middle of the bitinterval, a two (2) will result in a change in signal level after thebit interval, and a zero (0) will result in no change in signal level.This is a definition of the code word. It can also be said that a one(1) results in a change in signal level at the BEGINNING of the bitinterval and a two (2) in the MIDDLE of the bit interval. This issimilar to the place change of the numerals 1 and 0 of the NRZ-data.

It will be seen from the coding table that the modulated signal containssignal transitions or junctions with time intervals in steps of TB/2,although never less than 1TB and never more than 4TB.

The code word is transmitted differentially, such that the NRZ-signal inthe second row of the code table (01) is modulated to 0011 when thepreceding bit is 0, or to 1100 when the preceding bit is 1.

Synchronization is achieved because, in the resultant bit stream, whichis composed of the code words, the sequence 10101 (binary) is unique forthree consecutive ones (111) in the original NRZ-signal. This fact isutilized by the receiver (the decoder) for determining the phaseposition of the incoming bit stream.

DESCRIPTION OF PREFERRED EMBODIMENTS

The method according to the present invention will now be described inmore detail with reference to the accompanying drawings, in which

FIGS. 1, 2a, 2b, 2c, 2d and 3 illustrate the modulation of signal levelat different conceivable sequences of logic ones and zeroes in thedigital input signal;

FIG. 4 illustrates an exemplifying coder arrangement by means of whichthe coding method can be carried out and which lies within the scope ofthe invention; and

FIG. 5 illustrates an exemplifying decoder arrangement by means of whichthe decoding method can be carried out and which lies within the scopeof the invention.

The binary input signal B is illustrated in the Figures by differentsequences of logic ones, 1, and zeroes, 0, that can occur. The code wordsequence C (expressed with the base 3) is given during each such binarysignal, this sequence being used in the inventive method. Shown beneaththese sequencies is the resultant digital signal D, which in theillustrated and described preferred embodiment of the invention has beenmodulated in accordance with the inventive method in a manner such thatthe highest and the lowest frequency will be 2/TB and 1/STBrespectively. The reference sign and magnitude TB signifies respectivelya bit interval and the duration in seconds respectively of a data bit.Shown on the bottom line in each of FIGS. 1-3 are the values of theintegral RDS (Run Length Digital Sum), which according to the methodshall be equal to zero within a period of 4TB.

FIG. 1 shows a selected binary signal B which contains a sequence oflogic ones, 1, i.e. each bit interval TB consists of a logic one.According to the invention, such a sequence of logic ones is modulatedwith code word C, which in FIG. 1, and also in the Figures followingFIG. 1, is expressed as a trinary, and results in the digital signal D.Thus, a logic one is coded as a change in the middle of each bitinterval TB when this logic one is preceded by another logic one. Thisis presented as case I in the Coding Table presented above.

FIG. 2a illustrates case II according to the Coding Table, in which azero is followed by a one. Thus, the digital signal D is modulated by achange in signal level after the bit interval TB in which the logic zerooccurs. If the selected binary signal B contains a sequence of two logiczeroes followed by a logic one, as illustrated in FIG. 2b and presentedas case III in the Coding Table, the digital signal D is modulated by achange in signal level in the middle of the bit interval TB thatincludes the second logic zero.

FIG. 2c illustrates a conceivable coding possibility when the selectedbinary signal B includes a sequence of three logic zeroes which arefollowed by a logic one. In this case, the coding is obtained bymodulating the digital signal D such as to present a change of itssignal level after each bit interval TB that includes a logic zero.However, it has been found more advantageous to modulate the digitalsignal D such as to present a change in signal level after the secondbit interval TB that includes a zero, as will be seen from FIG. 2d andillustrated with case IV in the Coding Table presented above.

In those instances when the selected binary signal B includes a sequenceof more than three zeroes prior to a subsequent one, case V in theCoding Table presented above, the digital signal D is modulated inaccordance with the present invention such as to present a change in itssignal level at both the middle of the second bit interval TB and at theend of the third bit interval TB. This is shown in FIG. 3.

In order to illustrate how the inventive method can be realized, acoding arrangement and a decoding arrangement will now be described withreference to FIGS. 4 and 5. It will be understood, however, that thesetwo arrangements are merely given by way of example only and that themethod can be practiced equally as well with other arrangements or witha modified arrangement.

CODER

A coding arrangement by means of which the inventive method can becarried out includes a code word counter 1, a shift register 2, afeedback-connected flip-flop 3 and a combinatory logic 4 which forms acode word table. The code word counter 1 is constructed to count-up onestep for each pulse and if the counter counts-up from 3, it willbecome 1. It can only be zero when set to zero. (Zero setting0-1-2-3-1-2-3-1-2-3-1). Incoming bit streams are detected at a rate of1/TB. The shift register 2 and the feedback-connected flip-flop 3 areclock controlled at 2/TB. The code word counter 1 is clock controlled ata rate of 1/TB.

At the beginning of a coding process, the shift register 2 is set to10101010, which is the state to which it would be set after fourNRZ-ones (1111), in order to enable the receiver (the decoder in FIG. 5)to be able to find the correct phase position in the modulated signal D.When an incoming data bit is a logic one (1), the code word is read inthat row to which the code word counter 1 points and this code word isinserted in the shift register 2, whereafter the code word counter 1 isset to zero. When the incoming data bit is zero (0) and the code wordcounter 1 is numeral 3, the code word is read in line 3+ and this codeword is introduced into the shift register 2 with a displacement orshift of two steps. When the incoming data word is zero (0), the codeword counter 1 counts-up one step. Only the logic ones of the code wordC (FIGS. 1-3) need be written into the shift register 2, since a logiczero is clocked into the least significant bit in each clock cycle.

The feedback-connected flip-flop 3 is advantageously coupled back via anXOR-gate 6.

DECODER

An arrangement for regenerating a selected binary signal B from amodulated signal D includes a code word counter 11, a shift register 12,two flip-flops 17, 18, a phase-locked loop (DPLL) 16 and combinatorylogic which forms code word table 14, a comparator 13 and asynchronizing detector 15. The construction of the code word counter 11coincides with the construction of the code word counter 1 in the coderarrangement. One of the aforesaid flip-flops is a RXC flip-flop 17which, in response to a signal from the synchronizing detector 15, isintended to activate an output flip-flop 18 from which the regeneratedselected binary signal B can be obtained. The shift register 12 and theRXC flip-flop 17 are clock controlled at a rate of 2/TB. The code wordcounter 11 and the output flip-flop 18 are clock controlled at a rate of1/TB.

The incoming signal D, which consists of a signal modulated inaccordance with the method (ADPC High Density Pulse Code) is deliveredto the digital phase-locked loop (DPPL) 16 which is operated at afrequency which is several times higher than the frequency of theincoming signal D (e.g. 16/TB). When the signal is detected, there isproduced on the output of the DPLL-loop 16 a clock signal (2/TB) whichis in phase with the incoming signal D. The clock signal 2/TB is used toclock the coded signal D into the shift register 12. When the last fivebits in the shift register 12 are 10101, the flip-flop of thesynchronizing detector 15 flips, wherein the RXC flip-flop 17 isactivated and produces a clock signal having the frequency 1/TB, whichis in phase with the regenerated binary signal B. The code wordindicated by the code word counter 11 is compared with the content ofthe shift register 12 in each RXC cycle. If the code word coincides withthe content of the shift register, a logic one (1) is clocked into theoutput flip-flop 18 and the code word counter 11 is set to zero. Ifthere is no such coincidence, a logic zero (0) is clocked into theoutput flip-flop 18 and the setting of the shift register 12 iscontrolled so as to coincide with the beginning of a longer code wordor, when the code word counter 11 is 3, so that the shift register 12contains the code word in the line (3+) according to the above describedCoding Table. If an error is detected, the synchronizing flip-flop 15 isreset and the decoder again searches for the synchronizing pattern.

The described exemplifying coder/decoder embodiment is only suited foran NRZ-code which, in turn, is coded according to some supervisoryprotocol, for example with start and stop bits which are able todistinguish the original signal from the decoded signal when the decodedsignal is introduced by a number of logic ones (those that were used forsynchronization) and is terminated with logic zeroes. The terminatingzeroes can be avoided by delaying the NRZ-signal through a plurality ofseries-connected flip-flops (not shown).

The method can be extended with special code words which can be used formore advanced synchronization and control of a communication channel.

A full implementation for transferring blocks of binary data of selectedcontent and length in the form of a data package can be constructed inaccordance with the following, in which the code words are expressed inbase 3:

    ______________________________________                                        . . . 11111111    preamble                                                       22020111    beginning of frame type 1                                      or  22010201    beginning of frame type 2                                     or  22010120    beginning of frame type 3                                     or  22010010    beginning of frame type 4                                        xxxxxxxx    0-∞ number of data bits                                     22010202    end of frame mark                                                 02020020 . . . postamble                                                   ______________________________________                                    

Thus, a selected binary signal B can be transmitted with pronouncedbandwith limitation with the aid of the inventive method. The thusmodulated digital signal D is truly binary, having solely two levels.When practicing the present invention, there is obtained a bit-codedsignal of high information density, high power spectrum and narrowbandwidth, which we have accordingly designated HDPC, High Density PulseCode. The bit-code modulated signal contains no direct voltage componentand is, in itself, clock controlled. In the case of data communication,there is obtained with this bit-code modulated signal automatic (re-)synchronization and phase error detection. The inventive method iswell-suited for use within both data communcation and for storingdigital information. In the case of data communication, the method canbe used with both point-to-point and with bus (multidrop) connectionsand data can be transmitted continuously or in block form (datapackage).

It will be understood that the illustrated circuit constructiondescribed with reference to FIGS. 4 and 5 merely represents an exampleof how the inventive method can be realized. Each of the aforediscussedcoding and decoding functions can be integrated in a single logiccircuit. It will also be obvious to one of normal skill in this art thatthe method can be applied with other techniques which include sequentiallogic, with or without the aid of a read memory for translating bitpatterns, or as a state machine.

I claim:
 1. A method of producing a coded digital signal whichrepresents a selected binary signal having two logic states, whereby thecoded digital signal exhibits a continuous series of signal levelchanges and the two logic states of the selected binary signal are eachrepresented by a respective symmetric pulse train having frequencies f1and f2, thereby limiting the bandwidth of the selected binary signal,the method comprising the steps of:selecting a binary signal to be codedfor transmission, the binary signal having a certain data bit interval(TB); inputting the selected binary signal to a coder; counting bits inthe input binary signal and recognizing certain bit patterns accordingto a number of counted bits and their logic states in the input binarysignal; establishing a code word table in the coder having certain codewords for associating with said certain bit patterns; reading code wordsin the code table according to the recognized bit patterns; andproducing, according to the code words read from the code table, a codeddigital signal corresponding to said input binary signal wherein the twologic states of the binary signal are each represented by a symmetricpulse train one of which has a lower frequency f1 and the other having ahigher frequency f2, setting the higher frequency f2 equal to the numberof data bits transmitted each second divided by two Hertz (1/2TB), andcausing a transition between the two pulse trains to be such that therun length digital sum (RDS) of the coded digital signal is zero withinthe duration of three or four data bit intervals (3TB or 4TB).
 2. Amethod according to claim 1, wherein the coded digital signal isproduced as a truly binary signal having solely two levels.
 3. A methodaccording to claim 1, including producing the coded digital signal sothat a ratio between a longest and a shortest time lapse between twomutually sequential changes in signal level to be at most 4:1.
 4. Amethod according to claim 1, including producing the coded digitalsignal so that the time lapse between two mutually sequential changes insignal level is from 1 to 4 times the duration of a data bit interval(TB) in steps of 1/2 times the duration of a data bit interval.
 5. Amethod according to claim 1, including producing the coded digitalsignal in such a way that a sequence of logic ones in the input binarysignal produce a change in signal level in the middle of each bitinterval (TB) of the coded digital signal, and in that when a logic oneis preceded by a logic zero in the input binary signal, there is nochange in the signal level during the bit interval (TB) of the codeddigital signal.
 6. A method according to claim 1, including producingthe coded digital signal so that the occurrence of a single logic zero(0) followed by a one (1) in the input binary signal is represented inthe Coded digital signal as a change in signal level after that bitinterval (TB) in which the logic zero is included, and the occurrence oftwo logic zeroes (0) in a sequence which is followed by a one (1) in theinput binary signal is represented in the coded digital signal as achange in signal level in the middle of the bit interval (TB) thatincludes the second logic zero.
 7. A method according to claim 1,including producing the coded digital signal so that a sequence of threelogic zeroes (0) followed by a one (1) in the input binary signal isrepresented in the coded digital signal as a change in the signal levelafter each bit interval (TB) that includes a logic zero.
 8. A methodaccording to claim 1, including producing the coded digital signal sothat a sequence of three logic zeroes (0) followed by a one (1) in theinput binary signal is represented in the coded digital signal as achange in the signal level after the second bit interval (TB).
 9. Amethod according to claim 1, including a zero coding step wherein asequence of three logic zeroes (0) followed by at least a further zero(0) in the input binary signal is represented in the coded digitalsignal as a change in the signal level in the middle of that bitinterval (TB) which includes the second zero (0) and a further change inthe signal level at the end of that bit interval (TB) which includes thethird zero (0), and said zero coding step is repeated until fewer thanfour zeroes remain in the input binary signal.
 10. A coder for producinga coded digital signal which represents a selected binary signal havingtwo logic states, wherein the coded digital signal exhibits a continuousseries of changes in signal level and the two logic states of theselected binary signal are each represented by a respective symmetricalpulse train having frequencies f1 and f2, the coder comprising:codegeneration circuit means having an input responsive to the selectedbinary signal, for counting bits in the input binary signal andrecognizing certain bit patterns according to a number of counted bitsand their logic states in the input binary signal; the code generationcircuit means including a code word table having certain code words forassociation with said certain bit patterns; shift register means havingan input coupled to an output of the code generation circuit; an OR gatehaving one input coupled to said output of the code generation circuitmeans and a second input coupled to the input binary signal, and anoutput of said OR gate is coupled to a charging input of said shiftregister means; and a bistable circuit having an input coupled to anoutput of said shift register means, and an output from which the codeddigital signal can be obtained.